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K7B203625A 64kx36 synchronous sram - 1 - rev 3.0 december 1998 document title 64kx36-bit synchronous burst sram revision history rev. no. 0.0 0.1 1.0 2.0 3.0 history initial draft change dc characteristics. i cc value from 320ma to 250ma at -7. i cc value from 300ma to 230ma at -8. i cc value from 280ma to 200ma at -9. i sb value from 90ma to 70ma at -7. i sb value from 80ma to 60ma at -8. i sb value from 70ma to 50ma at -9. i sb1 value from 30ma to 20ma i sb2 value from 30ma to 20ma final spec release. add v ddq supply voltage( 2.5v ) min t oh parameter change : from 2.0ns to 3.0ns min t lzc parameter change : from 0ns to 3ns draft date july. 03. 1998 sep. 14. 1998 nov. 16. 1998 dec. 02. 1998 dec. 17. 1998 remark preliminary preliminary fianl final final the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to c hange the specifications. samsung electronics will evaluate and reply to your requests and questions on the parameters of this device. if you have any ques- tions, please contact the samsung branch office near your office, call or contact headquarters.
K7B203625A 64kx36 synchronous sram - 2 - rev 3.0 december 1998 we c we d fast access times parameter symbol -75 -80 -90 unit cycle time t cyc 8.5 10 12 ns clock access time t cd 7.5 8 9 ns output enable access time t oe 3.5 3.5 3.5 ns 64kx36-bit synchronous burst sram the K7B203625A is 2,359,296 bits synchronous static ran- dom access memory designed to support zero wait state per- formance for advanced pentium/power pc based system. and with cs 1 high, adsp is blocked to control signals. it can be organized as 64k words of 36 bits. and it integrates address and control registers, a 2-bit burst address counter and high output drive circuitry onto a single integrated circuit for reduced components counts implementation of high perfor- mance cache ram applications. write cycles are internally self-timed and synchronous. the self-timed write feature eliminates complex off chip write pulse shaping logic, simplifying the cache design and further reducing the component count. burst cycle can be initiated with either the address status pro- cessor( adsp ) or address status cache controller( adsc ) inputs. subsequent burst addresses are generated internally in the system s burst sequence and are controlled by the burst address advance( adv ) input. zz pin controls power down state and reduces stand-by cur- rent regardless of clk. the K7B203625A is implemented with samsung s high per- formance cmos technology and is available in a 100pin tqfp package. multiple power and ground pins are utilized to mini- mize ground bounce. general description features logic block diagram ? synchronous operation. ? on-chip address counter. ? write self-timed cycle. ? on-chip address and control registers. ? v dd = 3.3v +0.3v/-0.165v power supply. ? v ddq supply voltage 3.3v+0.3v/-0.165v for 3.3v i/o or 2.5v+0.4v/-0.125v for 2.5v i/o. ? 5v tolerant inputs except i/o pins. ? byte writable function. ? global write enable controls a full bus-width write. ? power down state via zz signal. ? asynchronous output enable control. ? adsp , adsc , adv burst control pins. ? lbo pin allows a choice of either a interleaved burst or a linear burst. ? three chip enables for simple depth expansion with no data contention. ? ttl-level three-state output. ? 100-tqfp-1420a clk lbo adv adsc adsp cs 1 cs 2 cs 2 gw bw we a we b oe zz dqa 0 ~ dqd 7 dqpa ~ dqpd burst control logic burst 64kx36 address control output data-in address counter memory array register register buffer logic c o n t r o l r e g i s t e r c o n t r o l r e g i s t e r a 0 ~a 1 a 0 ~a 1 a 2 ~a 15 a 0 ~a 15
K7B203625A 64kx36 synchronous sram - 3 - rev 3.0 december 1998 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 pin tqfp (20mm x 14mm) dqpc dqc 0 dqc 1 v ddq v ssq dqc 2 dqc 3 dqc 4 dqc 5 v ssq v ddq dqc 6 dqc 7 n.c. v dd n.c. v ss dqd 0 dqd 1 v ddq v ssq dqd 2 dqd 3 dqd 4 dqd 5 v ssq v ddq dqd 6 dqd 7 dqpd 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dqpb dqb 7 dqb 6 v ddq v ssq dqb 5 dqb 4 dqb 3 dqb 2 v ssq v ddq dqb 1 dqb 0 v ss n.c. v dd zz dqa 7 dqa 6 v ddq v ssq dqa 5 dqa 4 dqa 3 dqa 2 v ssq v ddq dqa 1 dqa 0 dqpa 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 a 6 a 7 c s 1 c s 2 w e d w e c w e b w e a c s 2 v d d v s s c l k g w b w o e a d s c a d s p a d v a 8 8 1 a 9 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 n . c . a 1 5 a 1 4 a 1 3 a 1 2 a 1 1 a 1 0 n . c . n . c . v d d v s s n . c . n . c . a 0 a 1 a 2 a 3 a 4 a 5 3 1 l b o pin name symbol pin name tqfp pin no. symbol pin name tqfp pin no. a 0 - a 15 adv adsp adsc clk cs 1 cs 2 cs 2 we x oe gw bw zz lbo address inputs burst address advance address status processor address status controller clock chip select chip select chip select byte write inputs output enable global write enable byte write enable power down input burst mode control 32,33,34,35,36,37, 44,45,46,47,48,49, 81,82,99,100 83 84 85 89 98 97 92 93,94,95,96 86 88 87 64 31 v dd v ss n.c. dqa 0 ~a 7 dqb 0 ~b 7 dqc 0 ~c 7 dqd 0 ~d 7 dqpa~pd v ddq v ssq power supply(+3.3v) ground no connect data inputs/outputs output power supply (2.5v or 3.3v) output ground 15,41,65,91 17,40,67,90 14,16,38,39,42,43,50,66 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76
K7B203625A 64kx36 synchronous sram - 4 - rev 3.0 december 1998 function description the K7B203625A is a synchronous sram designed to support the burst address accessing sequence of the pentium and power pc based microprocessor. all inputs (with the exception of oe , lbo and zz) are sampled on rising clock edges. the start and duration of the burst access is controlled by adsc , adsp and adv and chip select pins. when zz is pulled high, the sram will enter a power down state. at this time, internal state of the sram is preserved. when zz returns to low, the sram normally operates after 2cycles of wake up time. zz pin is pulled down internally. read cycles are initiated with adsp (or adsc ) using the new external address clocked into the on-chip address register when both gw and bw are high or when bw is low and we a, we b, we c, and we d are high. when adsp is sampled low, the chip selects are sampled active, and the output buffer is enabled with oe . the data of cell array accessed by the current address are projected to the output pins. write cycles are also initiated with adsp (or adsc ) and are differentiated into two kinds of operations; all byte write operation and individual byte write operation. all byte write occurs by enabling gw (independent of bw and we x.), and individual byte write is performed only when gw is high and bw is low. in K7B203625A, a 64kx36 organization, we a controls dqa0 ~ dqa7 and dqpa, we b controls dqb0 ~ dqb7 and dqpb, we c controls dqc0 ~ dqc7 and dqpc and we d controls dqd0 ~ dqd7 and dqpd. cs 1 is used to enable the device and conditions internal use of adsp and is sampled only when a new external address is loaded. adv is ignored at the clock edge when adsp is asserted, but can be sampled on the subsequent clock edges. the address increases internally for the next access of the burst when adv is sampled low. addresses are generated for the burst access as shown below, the starting point of the burst sequence is provided by the externa l address. the burst address counter wraps around to its initial state upon completion. the burst sequence is determined by the st ate of the lbo pin. when this pin is low, linear burst sequence is selected. and this pin is high, interleaved burst sequence is selected. burst sequence table (interleaved burst) lbo pin high case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 1 0 1 0 burst sequence table (linear burst) note : 1. lbo pin must be tied to high or low, and floating state must not be allowed. lbo pin low case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 1 0 asynchronous truth table (see notes 1 and 2) : operation zz oe i/o status sleep mode h x high-z read l l dq l h high-z write l x din, high-z deselected l x high-z notes 1. x means "don't care". 2. zz pin is pulled down internally 3. for write cycles that following read cycles, the output buffersmust be disabled with oe , otherwise data bus contention will occur. 4. sleep mode means power down state of which stand-by current does not depend on cycle time. 5. deselected means power down state of which stand-by current depends on cycle time.
K7B203625A 64kx36 synchronous sram - 5 - rev 3.0 december 1998 synchronous truth table notes : 1. x means "don t care". 2. the rising edge of clock is symbolized by - . 3. write = l means write operation in write truth table. write = h means read operation in write truth table. 4. operation finally depends on status of asynchronous input pins(zz and oe ). cs 1 cs 2 cs 2 adsp ads adv write clk address accessed operation h x x x l x x - n/a not selected l l x l x x x - n/a not selected l x h l x x x - n/a not selected l l x x l x x - n/a not selected l x h x l x x - n/a not selected l h l l x x x - external address begin burst read cycle l h l h l x l - external address begin burst write cycle l h l h l x h - external address begin burst read cycle x x x h h l h - next address continue burst read cycle h x x x h l h - next address continue burst read cycle x x x h h l l - next address continue burst write cycle h x x x h l l - next address continue burst write cycle x x x h h h h - current address suspend burst read cycle h x x x h h h - current address suspend burst read cycle x x x h h h l - current address suspend burst write cycle h x x x h h l - current address suspend burst write cycle write truth table notes : 1. x means "don t care". 2. all inputs in this table must meet setup and hold time around the rising edge of clk( - ). gw bw we a we b we c we d operation h h x x x x read h l h h h h read h l l h h h write byte a h l h l h h write byte b h l h h l l write byte c and d h l l l l l write all bytes l x x x x x write all bytes
K7B203625A 64kx36 synchronous sram - 6 - rev 3.0 december 1998 capacitance* (t a =25 c, f=1mhz) *note : sampled not 100% tested. parameter symbol test condition min max unit input capacitance c in v in =0v - 5 pf output capacitance c out v out =0v - 7 pf absolute maximum ratings* *notes : stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol rating unit voltage on v dd supply relative to v ss v dd -0.3 to 4.6 v voltage on v ddq supply relative to v ss v ddq v dd v voltage on input pin relative to v ss v in -0.3 to 6.0 v voltage on i/o pin relative to v ss v io -0.3 to v ddq + 0.5 v power dissipation p d 1.2 w storage temperature t stg -65 to 150 c operating temperature t opr 0 to 70 c storage temperature range under bias t bias -10 to 85 c operating conditions at 3.3v i/o (0 c t a 70 c) parameter symbol min typ. max unit supply voltage v dd 3.135 3.3 3.6 v v ddq 3.135 3.3 3.6 v ground v ss 0 0 0 v operating conditions at 2.5v i/o (0 c t a 70 c) parameter symbol min typ. max unit supply voltage v dd 3.135 3.3 3.6 v v ddq 2.375 2.5 2.9 v ground v ss 0 0 0 v
K7B203625A 64kx36 synchronous sram - 7 - rev 3.0 december 1998 dc electrical characteristics (t a =0 to 70 c, v dd =3.3v +0.3v/- 0.165v) * v il (min)=-2.0(pulse width t cyc / 2) ** v ih (max)=4.6(pulse width t cyc / 2) ** in case of i/o pins, the max. v ih =v ddq +0.5v parameter symbol test conditions min max unit input leakage current(except zz) i il v dd =max , v in =v ss to v dd -2 +2 m a output leakage current i ol output disabled, v out =v ss to v ddq -2 +2 m a operating current i cc device selected, i out =0ma, zz v il , all inputs=v il or v ih cycle time 3 t cyc min -75 - 250 ma -80 - 230 -90 - 200 standby current i sb device deselected, i out =0ma, zz v il , f=max, all inputs 0.2v or 3 v dd -0.2v -75 - 70 ma -80 - 60 -90 - 50 i sb1 device deselected,i out =0ma, zz 0.2v, f=0, all inputs=fixed (v dd -0.2v or 0.2v) - 20 ma i sb2 device deselected, i out =0ma, zz 3 v dd -0.2v, f=max, all inputs v il or 3 v ih - 20 ma output low voltage(3.3v i/o) v ol i ol = 8.0ma - 0.4 v output high voltage(3.3v i/o) v oh i oh = -4.0ma 2.4 - v output low voltage(2.5v i/o) v ol i ol = 1.0ma - 0.4 v output high voltage(2.5v i/o) v oh i oh = -1.0ma 2.0 - v input low voltage(3.3v i/o) v il -0.5* 0.8 v input high voltage(3.3v i/o) v ih 2.0 v dd +0.5** v input low voltage(2.5v i/o) v il -0.3* 0.7 v input high voltage(2.5v i/o) v ih 1.7 v dd +0.5** v test conditions parameter value input pulse level(for 3.3v i/o) 0 to 3v input pulse level(for 2.5v i/o) 0 to 2.5v input rise and fall time(measured at 0.3v and 2.7v for 3.3v i/o) 1ns input rise and fall time(measured at 0.3v and 2.1v for 2.5v i/o) 1ns input and output timing reference levels for 3.3v i/o 1.5v input and output timing reference levels for 2.5v i/o v ddq /2 output load see fig. 1 (v dd =3.3v+0.3v/-0.165v , v ddq =3.3v+0.3/-0.165v or v dd =3.3v+0.3v/-0.165v , v ddq =2.5v+0.4v/-0.125v, t a =0 to 70 c)
K7B203625A 64kx36 synchronous sram - 8 - rev 3.0 december 1998 ac timing characteristics (t a =0 to 70 c, v dd =3.3v + 0.3v/-0.165v) notes : 1. all address inputs must meet the specified setup and hold times for all rising clock edges whenever adsc and/or adsp is sampled low and cs is sampled low. all other synchronous inputs must meet the specified setup and hold times whenever this device is chip select ed. 2. both chip selects must be active whenever adsc or adsp is sampled low in order for the this device to remain enabled. 3. adsc or adsp must not be asserted for at least 2 clock after leaving zz state. 4. at any given voltage and temperature, t hzc is less than t lzc. parameter symbol -75 -80 -90 unit min max min max min max cycle time t cyc 8.5 - 10 - 12 - ns clock access time t cd - 7.5 - 8 - 9 ns output enable to data valid t oe - 3.5 - 3.5 - 3.5 ns clock high to output low-z t lzc 3 - 3 - 3 - ns output hold from clock high t oh 3 - 3 - 3 - ns output enable low to output low-z t lzoe 0 - 0 - 0 - ns output enable high to output high-z t hzoe - 3.5 - 3.5 - 3.5 ns clock high to output high-z t hzc 2 3.5 2 3.5 2 3.5 ns clock high pulse width t ch 3 - 4 - 4.5 - ns clock low pulse width t cl 3 - 4 - 4.5 - ns address setup to clock high t as 2.0 - 2.0 - 2.0 - ns address status setup to clock high t ss 2.0 - 2.0 - 2.0 - ns data setup to clock high t ds 2.0 - 2.0 - 2.0 - ns write setup to clock high ( gw , bw , we x ) t ws 2.0 - 2.0 - 2.0 - ns address advance setup to clock high t advs 2.0 - 2.0 - 2.0 - ns chip select setup to clock high t css 2.0 - 2.0 - 2.0 - ns address hold from clock high t ah 0.5 - 0.5 - 0.5 - ns address status hold from clock high t sh 0.5 - 0.5 - 0.5 - ns data hold from clock high t dh 0.5 - 0.5 - 0.5 - ns write hold from clock high ( gw , bw , we x ) t wh 0.5 - 0.5 - 0.5 - ns address advance hold from clock high t advh 0.5 - 0.5 - 0.5 - ns chip select hold from clock high t csh 0.5 - 0.5 - 0.5 - ns zz high to power down t pds 2 - 2 - 2 - cycle zz low to power up t pus 2 - 2 - 2 - cycle output load(b) (for t lzc , t lzoe , t hzoe & t hzc ) dout 5pf* fig. 1 * including scope and jig capacitance output load(a) dout z0=50 w * capacitive load consists of all components of 30pf* the test environment. rl=50 w 353 w / 1538 w +3.3v for 3.3v i/o 319 w / 1667 w vl=1.5v for 3.3v i/o v ddq /2 for 2.5v i/o /+2.5v for 2.5v i/o
K7B203625A 64kx36 synchronous sram - 9 - rev 3.0 december 1998 c l o c k a d s p a d s c a d d r e s s w r i t e c s a d v o e d a t a o u t t i m i n g w a v e f o r m o f r e a d c y c l e n o t e s : w r i t e = l m e a n s g w = l , o r g w = h , b w = l , w e x . = l c s = l m e a n s c s 1 = l , c s 2 = h a n d c s 2 = l c s = h m e a n s c s 1 = h , o r c s 1 = l a n d c s 2 = h , o r c s 1 = l , a n d c s 2 = l t c h t c l t s s t s h t s s t s h t a s t a h a 1 a 2 a 3 b u r s t c o n t i n u e d w i t h n e w b a s e a d d r e s s t w s t w h t c s s t c s h t a d v s t a d v h t o e t h z o e t l z o e t c d t o h ( a d v i n s e r t s w a i t s t a t e ) t h z c q 3 - 4 q 3 - 3 q 3 - 2 q 3 - 1 q 2 - 4 q 2 - 3 q 2 - 2 q 2 - 1 q 1 - 1 d o n t c a r e u n d e f i n e d t c y c
K7B203625A 64kx36 synchronous sram - 10 - rev 3.0 december 1998 c l o c k a d s p a d s c a d d r e s s w r i t e c s a d v d a t a i n o e d a t a o u t t c h t c l t s s t s h t a s t a h a 1 a 2 a 3 ( a d s c e x t e n d e d b u r s t ) t l z o e d 2 - 1 d 1 - 1 t c s s t c s h ( a d v s u s p e n d s b u r s t ) d 2 - 2 d 2 - 3 d 2 - 4 d 3 - 1 d 3 - 2 d 3 - 3 d 2 - 2 d 3 - 4 q 0 - 3 q 0 - 4 t s s t s h t w s t w h t a d v s t a d v h t d s t d h t i m i n g w a v e f o r m o f w r t e c y c l e d o n t c a r e u n d e f i n e d t c y c
K7B203625A 64kx36 synchronous sram - 11 - rev 3.0 december 1998 t i m i n g w a v e f o r m o f c o m b i n a t i o n r e a d / w r t e c y c l e ( a d s p c o n t r o l l e d , a d s c = h i g h ) c l o c k a d s p a d d r e s s w r i t e c s a d v o e d a t a o u t t c h t c l t d s t d h q 3 - 3 d a t a i n t o e t o h a 1 a 2 a 3 d 2 - 1 q 3 - 1 q 3 - 2 q 3 - 4 t s s t s h t a s t a h t w s t w h t a d v s t a d v h t l z o e t h z o e t c d t h z c t l z c d o n t c a r e u n d e f i n e d t c y c q 1 - 1
K7B203625A 64kx36 synchronous sram - 12 - rev 3.0 december 1998 t i m i n g w a v e f o r m o f s i n g l e r e a d / w r i t e c y c l e ( a d s c c o n t r o l l e d , a d s p = h i g h ) c l o c k a d s c a d d r e s s w r i t e c s a d v o e d a t a i n t c h t c l t h z o e d 6 - 1 d a t a o u t t w s t w h t c d t o h t o e d 5 - 1 d 7 - 1 t w s t w h t l z o e t d h t d s a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 q 3 - 1 q 1 - 1 q 2 - 1 q 4 - 1 q 8 - 1 q 9 - 1 t c s s t c s h t s s t s h d o n t c a r e u n d e f i n e d t c y c
K7B203625A 64kx36 synchronous sram - 13 - rev 3.0 december 1998 d 7 - 1 t i m i n g w a v e f o r m o f s i n g l e r e a d / w r i t e c y c l e ( a d s p c o n t r o l l e d , a d s c = h i g h ) c l o c k a d s p a d d r e s s w r i t e c s a d v o e d a t a i n t c h t c l t h z o e d a t a o u t t a s t a h t c d t o h t o e d 5 - 1 t l z o e t d h t d s a 1 a 2 a 3 a 4 a 5 a 6 a 9 q 3 - 1 q 1 - 1 q 2 - 1 q 4 - 1 q 8 - 1 q 9 - 1 t c s s t c s h t s s t s h a 7 a 8 d 6 - 1 d o n t c a r e u n d e f i n e d t c y c
K7B203625A 64kx36 synchronous sram - 14 - rev 3.0 december 1998 t i m i n g w a v e f o r m o f p o w e r d o w n c y c l e c l o c k a d s p a d d r e s s w r i t e c s a d v d a t a i n t c h t c l d 2 - 2 o e t w h t h z o e t l z o e d 2 - 1 a 1 t s s t s h d a t a o u t t p u s a 2 a d s c q 1 - 1 z z t a s t a h t c s s t c s h t o e t h z c t p d s s l e e p s t a t e z z s e t u p c y c l e n o r m a l o p e r a t i o n m o d e z z r e c o v e r y c y c l e t w s d o n t c a r e u n d e f i n e d t c y c
K7B203625A 64kx36 synchronous sram - 15 - rev 3.0 december 1998 application information the samsung 64kx36 synchronous burst sram has two additional chip selects for simple depth expansion. depth expansion this permits easy secondary cache upgrades from 64k depth to 128k depth without extra logic. data address clk ads microprocessor cs 2 cs 2 clk adsc we x oe cs 1 address data adv adsp 64kx36 sb sram (bank 0) cs 2 cs 2 clk adsc we x oe cs 1 address data adv adsp 64kx36 sb sram (bank 1) clk address cache controller a [0:16] a [16] a [0:15] a [ 16 ] a [ 0:15 ] i/o [0:71] 64-bits clock adsp address data out interleave read timing (refer to non-interleave write timing for interleave write timing) bank 0 is selected by cs 2 , and bank 1 deselected by cs 2 q1-1 q1-2 q1-4 q1-3 oe data out t ss t sh a1 a2 write cs 1 a n+1 adv (bank 0) (bank 1) q2-1 q2-2 q2-4 q2-3 t as t ah t css t csh t ws t wh t advs t advh t oe t lzoe t hzc bank 0 is deselected by cs 2 , and bank 1 selected by cs 2 [0:n] don t care undefined t cd t lzc *notes n = 14 32k depth, 15 64k depth, 16 128k depth ( adsp controlled , adsc =high)
K7B203625A 64kx36 synchronous sram - 16 - rev 3.0 december 1998 0.10 max 0~8 22.00 0.30 20.00 0.20 16.00 0.30 14.00 0.20 1.40 0.10 1.60 max 0.05 min (0.58) 0.50 0.10 #1 (0.83) 0.50 0.10 100-tqfp-1420a 0.65 0.30 0.10 0.10 max + 0.10 - 0.05 0.127 package dimensions units:millimeters/inches

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